AMD’s Accelerated Processor Unit (APU) chips integrate CPU and GPU in a single chip (as shown in Figure 6.1(c)). AMD’s Athlon 64 and later Intel’s Nehalem architectures reduced the latency associated with main memory access by integrating the memory controller in the CPU die (as shown in Figure 6.1(b)). Figure 6.1(a) represents a typical arrangement for discrete GPU solutions. The existing architectures are shown in Figure 6.1. Only some low-cost, entry-level systems violate this rule by having a portion of the main memory allocated for display and GPU purposes at the expense of performance, since CPU and GPU compete for memory access. GPU program deployment has a characteristic that can be considered a major obstacle: GPU and host memories are typically disjoint, requiring explicit (or implicit, depending on the development platform) data transfer between the two. ![]() Going from a handful to thousands of threads requires a different way of partitioning and processing loads. This obviously mandates a shift in the programming paradigm we employ. ![]() Even more are needed so that computation can be overlapped with memory transfers. In order to put all this computational power to use, we must create at least one separate thread for each core. This results in having hundreds or thousands (!) of cores in contemporary GPUs, as shown in Section 1.3.2. Learn to use a step-by-step approach in the development of CUDA programs via the development of two case studies.Ħ.1 GPU PROGRAMMING GPUs devote a big portion of their silicon real estate to compute logic, compared to conventional CPUs that devote large portions of it to on-chip cache memory.Combine CUDA and MPI to handle big workloads over a cluster of GPU-equipped machines.Learn how to use streams and zero-copy memory to maximize the utilization of a GPU.Learn how computations are mapped to threads in Compute Unified Device Architecture (CUDA) using grids and blocks.Understand the memory hierarchy of GPUs and how the different memories can be utilized.
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